Field
This disclosure relates generally to semiconductor packages including multiple die, and more specifically, to interconnections between multiple die of a semiconductor package.
Related Art
Higher performance, lower costs, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the semiconductor industry. Obtaining greater integrated circuit density is primarily limited by the space or “real estate” available for mounting die on a substrate, especially when multiple die are mounted. Known packaging technologies provide for simple flip chip attachment of one or more die to a substrate or wire bond attachment of one or more die to a substrate.
The number of connections between adjacent die in the same package are limited by package design rules and less so by die design rules, which govern minimum pad, line, or space widths. One approach for increasing the number of connections between adjacent die, such as between flip chip die attached to a substrate, is adding substrate layers to implement connections through the substrate between the die, which increases cost.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements, unless otherwise noted. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.